Testing a semiconductor chip device (e.g., a device under test (DUT)) using a full pin count functional tester (tester) that mimics the remaining components of the devices is commonplace in the chip industry. As a DUT resets and fetches data from memory, the tester provides all the controls and instructions that are necessary for the DUT to operate properly. The tester also compares how the DUT behaves with pre-simulated behavior to detect faulty or slow circuits on the DUT. However, a prerequisite for testing is a high speed, high performance tester that is compatible with the DUT, both in bandwidth as well as signaling technologies.
High performance, full pin count testers are becoming increasingly more expensive and cost prohibitive in the competitive and low margin chip market. Furthermore, as a practical matter, customized testers are not timely available for use, since typically only short time windows are available for manufacturing and testing a DUT. These short time windows make it impractical that a customized tester be made available for timely testing. Moreover, it is not practical to design or purchase a customized tester for each class of DUTs. Correspondingly, it has become increasingly more popular to perform testing on a DUT on legacy testers having limited pin counts and slower performances than the DUT.
One conventional technique loads a cache with instructions and data for permitting the processor to execute directly from the cache, without bus access. This technique allows a legacy tester to be used for loading the cache with a low speed test port (shared with the functional pins). This removes the need for a full speed, full pin count tester, so that testing can be performed on the tester for a DUT having a much higher clock speed. Although this technique permits testing to be conducted in the first instance, it still does not address problems associated with testing for cache paging or other bus transactions. Cache paging and bus transactions are necessary for testing memory management and bus logic that is an increasing part of modern complex microprocessor architectures.
The technique described above that executes diagnostic tests directly from a cache of a DUT is referred to as a structural based functional test (SBFT). Thus, a SBFT needs to avoid sending any read/write cycles to the bus, since there may be no tester pins for performing the necessary handshaking in order for a bus transaction to be completed. Alternatively, the bus can be supplied by the tester to the DUT using a limited number of tester pins and de-multiplexing the full pin count of the DUT. But this de-multiplexing interaction can substantially slow the throughput of the test, and not adequately test the highest speed with which the bus should be functioning. A similar situation exists for a functional random instruction test for speed (FRITS) (random instructions during test (FRITS) versus programmed instructions during test used with (SBFT)).
Therefore, there is a need for improved bus interactions between a DUT and a tester.